A conventional contact process for a power MOS device is considerably simple and is performed including heavily doping N+ source and P+ contact region for good ohm contact to reduce the contact resistance between the silicon material of the source and the metal thereof. In this process, the masks to define the N+ region for the source and to define the contact hole are required to overlap well with each other for the formation of good ohm contact.
FIGS. 1A–1G illustrate a conventional contact process for a source contact of an N-type trench power MOSFET. As shown in FIG. 1A, a power MOSFET contains an N− epitaxial layer 12 on an N+ substrate 10, and on the N− epitaxial layer 12, a gate 16 as well as a P-type base region 14 are formed. The contact process comprises defining and implanting an N+ region 18 for the source with a mask 20, and typically, arsenic (As) is implanted thereto and then thermally driven in to diffuse to be the N+ region 18, as shown in FIG. 1B.
Subsequently, as shown in FIG. 1C, an insulator 22 preferably of NSG/BPSG is deposited and annealed. Then, a contact hole 26 is defined with a mask 24 and etched, as shown in FIG. 1D. Afterward, a P+ region 28 is implanted for example with boron difluoride (BF2) through the contact hole 26, as shown in FIG. 1E.
In FIG. 1F, annealing and blanket etching are performed to smooth the insulator 22 and to remove the defective surfaces of the N+ region 18 and the P+ region 28. Finally, metals 30 and 32 are deposited for the source and drain electrodes, as shown in FIG. 1G.
In such structure of a power MOS, the extended length of the N+ junction resulted from the lateral diffusion is nearly the same as the depth thereof by vertically driven in, such that the actual length of the N+ region is much greater than the length defined by the source N+ mask. For the power MOS, in addition to the limitation of the scale down to the unit cell of the power MOS by the longer source N+ region, the current capability of the device itself is reduced, resulting in second breakdown of the trench power MOSFET and latch-up of the insulated-gate bipolar transistor (IGBT).